Fundamental to the successful operation of a digital communication system, such as the digital fiber optic communication system diagrammatically illustrated in FIG. 1, is its ability to recover clock and perform error detection at the receiver site. In order to optimize efficiency and reduce cost, it is common practice to combine an incoming digital data stream 11 and a clock signal 13 into a composite signal. The composite signal is produced by a transmit/encoder 15 and is transmitted either `as is`, or further encoded (e.g. scrambled/encrypted). The encoded signal is used to digitally modulate a carrier, such as laser output beam which is conveyed over a fiber optic channel 17 to a downstream receiver site 21. At the receiver site 21, the digitally modulated light beam is processed to extract, or recover, each of the embedded clock signal and data.
In order to maintain accurate operation and maximum sensitivity of the signal receiving circuitry, it is necessary that the transmitted digital data stream be as D.C.-balanced as possible. In addition, communication system users customarily require that the recovered clock exhibit minimum clock asymmetry. Because of these requirements, integrated clock and data encoding schemes have customarily involved the use of complex signal processing algorithms, which are often data rate specific, entailing costly circuit designs.
One prior art digital encoding technique for accommodating a variation in the rate of the clock signal onto which data is to be digitally encoded is described in the Chi U.S. Pat. No. 4,954,825, entitled "Self Clocking Binary Data Encoding/Decoding Method," issued Sep. 4, 1990, and companion U.S. Pat. Nos. 4,951,049 and 5,025,328. Although not characterized as being employed in digital data transmission systems, but rather being directed to solving the problem of variations in speed of movement of a digital recording medium past a read/write transducer (such as a magnetic recording/reproduction head), the digital encoding technique of Chi accommodates variations in clock rate by the use of a derivative encoding-extraction technique. This derivative technique is clock edge polarization sensitive, whereby the full cycle boundaries of each clock signal will be read out with a well demarcated polarization and amplitude, on the one hand, whereas encoded data modulation between the full cycle clock edges will either have an opposite polarity (for a first binary value, e.g. `1`) or have a very reduced amplitude (for a second binary value, e.g. `0`). Also, the location of the data modulation is sufficiently displaced relative to the full cycle clock boundaries, so that clock and data are separately identifiable.
More particularly, with reference to FIG. 2, which corresponds to FIG. 1 of the above-referenced '825 Chi patent, in order to produce an encoded clock signal with a data bit of a first binary value, `1` for example, a single high-to-low transition occurs between the low-to-high clock cycle boundary transitions. On the other hand, to encode a data bit of a second, complementary binary value, `0` for example, the interior portion of the event cell undergoes a plurality of (high-to-low/low-to-high) transitions between the low-to-high clock transitions that bound the opposite ends of the event cell.
Because of the nature of the operation of the sensing transducer (such as a magnetic head) in the recording/playback circuitry, the plurality of closely spaced high-to-low/low-to-high transitions between the positive polarity transitions in the clock signal effectively destructively combine to produce a minimum amplitude output signal, associated with a binary value of `0`, as shown by the read waveform. On the other hand, for the complementary data value of `1`, since its associated single transition within an event cell has no immediately adjacent opposite polarity transition to reduce its amplitude when differentially sensed, a well demarcated negative polarity output pulse is produced. Similarly, since the end boundary of each clock cycle or event cell is also defined by only a single (positive polarity, or low-to-high) transition, and has no immediately adjacent opposite polarity transition to reduce its amplitude when differentially sensed, a well demarcated positive polarity pulse is produced. Thus, on read-out, positive polarity pulses are detected as clock cycle boundaries, negative polarity pulses are detected as `1` bits, and very reduced amplitude values between clock cycle boundaries are detected as `0` bits.
As noted above, even though the binary clock encoding scheme described in the Chi patent embeds data in the clock signal and allows for variations in clock rate, it is designed for use in a signal recording/playback device having derivative-based signal recovery, and is not readily suitable for digital data communications. Shortcomings of the patented encoding mechanism to digital communications include the fact that each event cell of the data-embedded clock stream occupies a complete clock cycle. This, coupled with its use of a derivative-based encoding mechanism, results in a D.C. level that is prone to depart significantly from zero, and also prevents quality (bit error rate) monitoring and sub-rate channel signalling.